/* * Copyright (c) 2012 The Linux Foundation. All rights reserved.* */


#ifndef _GMAC_CLOCK_H_
#define _GMAC_CLOCK_H_
 
//#define MSM_CLK_CTL_BASE 			0xFA010000
#define NSS_RESET_ADDR				(0x40000000)
#define NSS_REG(off)         			(MSM_CLK_CTL_BASE + (off))
#define MDC_CLK_DIV				0

#define NSS_RESET_SPARE				NSS_REG(0x3B60)
#define NSSFB0_CLK_SRC_CTL			NSS_REG(0x3B80)
#define NSSFB0_CLK_SRC0_NS			NSS_REG(0x3B84)
#define NSSFB0_CLK_SRC1_NS			NSS_REG(0x3B88)
#define NSSFB0_CLK_CTL				NSS_REG(0x3BA0)
#define NSSFAB_GLOBAL_BUS_NS			NSS_REG(0x3BC0)
#define NSSFB1_CLK_SRC_CTL			NSS_REG(0x3BE0)
#define NSSFB1_CLK_SRC0_NS			NSS_REG(0x3BE4)
#define NSSFB1_CLK_SRC1_NS			NSS_REG(0x3BE8)
#define NSSFB1_CLK_CTL				NSS_REG(0x3C00)
#define UBI32_MPT0_CLK_CTL			NSS_REG(0x3C40)
#define UBI32_MPT1_CLK_CTL			NSS_REG(0x3C44)
#define CE5_HCLK_SRC_CTL			NSS_REG(0x3C60)
#define CE5_HCLK_SRC0_NS			NSS_REG(0x3C64)
#define CE5_HCLK_SRC1_NS			NSS_REG(0x3C68)
#define CE5_HCLK_CTL				NSS_REG(0x3C6C)
#define NSSFPB_CLK_CTL				NSS_REG(0x3C80)
#define NSSFPB_CLK_SRC_CTL			NSS_REG(0x3C84)
#define NSSFPB_CLK_SRC0_NS			NSS_REG(0x3C88)
#define NSSFPB_CLK_SRC1_NS			NSS_REG(0x3C8C)
#define GMAC_CORE1_CLK_SRC_CTL			NSS_REG(0x3CA0)
#define GMAC_CORE1_CLK_SRC0_MD			NSS_REG(0x3CA4)
//#define GMAC_COREn_CLK_SRC1_MD(n)		NSS_REG(0x3CA8+32*(n-1))
#define GMAC_CORE1_CLK_SRC1_MD			NSS_REG(0x3CA8)
//#define GMAC_COREn_CLK_SRC0_NS(n)		NSS_REG(0x3CAC+32*(n-1))
#define GMAC_CORE1_CLK_SRC0_NS			NSS_REG(0x3CAC)
//#define GMAC_COREn_CLK_SRC1_NS(n)		NSS_REG(0x3CB0+32*(n-1))
#define GMAC_CORE1_CLK_SRC1_NS			NSS_REG(0x3CB0)
//#define GMAC_COREn_CLK_CTL(n)			NSS_REG(0x3CB4+32*(n-1))
#define GMAC_CORE1_CLK_CTL			NSS_REG(0x3CB4)
//#define GMAC_COREn_CLK_FS(n)			NSS_REG(0x3CB8+32*(n-1))
#define GMAC_CORE1_CLK_FS			NSS_REG(0x3CB8)
//#define GMAC_COREn_RESET(n)			NSS_REG(0x3CBC+32*(n-1))
#define GMAC_CORE1_RESET			NSS_REG(0x3CBC)
#define UBI32_COREn_CLK_SRC_CTL(n)		NSS_REG(0x3D20+32*(n-1))
#define UBI32_CORE1_CLK_SRC_CTL			NSS_REG(0x3D20)
#define UBI32_COREn_CLK_SRC0_MD(n)		NSS_REG(0x3D24+32*(n-1))
#define UBI32_CORE1_CLK_SRC0_MD			NSS_REG(0x3D24)
#define UBI32_COREn_CLK_SRC1_MD(n)		NSS_REG(0x3D28+32*(n-1))
#define UBI32_CORE1_CLK_SRC1_MD			NSS_REG(0x3D28)
#define UBI32_COREn_CLK_SRC0_NS(n)		NSS_REG(0x3D2C+32*(n-1))
#define UBI32_CORE1_CLK_SRC0_NS			NSS_REG(0x3D2C)
#define UBI32_COREn_CLK_SRC1_NS(n)		NSS_REG(0x3D30+32*(n-1))
#define UBI32_CORE1_CLK_SRC1_NS			NSS_REG(0x3D30)
#define UBI32_COREn_CLK_CTL(n)			NSS_REG(0x3D34+32*(n-1))
#define UBI32_CORE1_CLK_CTL			NSS_REG(0x3D34)
#define UBI32_COREn_CLK_FS(n)			NSS_REG(0x3D38+32*(n-1))
#define UBI32_CORE1_CLK_FS			NSS_REG(0x3D38)
#define UBI32_COREn_RESET_CLAMP(n)		NSS_REG(0x3D3C+32*(n-1))
#define UBI32_CORE1_RESET_CLAMP			NSS_REG(0x3D3C)
#define NSS_250MHZ_CLK_SRC_CTL			NSS_REG(0x3D60)
#define NSS_250MHZ_CLK_SRC0_NS			NSS_REG(0x3D64)
#define NSS_250MHZ_CLK_SRC1_NS			NSS_REG(0x3D68)
#define NSS_250MHZ_CLK_SRC0_MD			NSS_REG(0x3D6C)
#define NSS_250MHZ_CLK_SRC1_MD			NSS_REG(0x3D70)
#define NSS_250MHZ_CLK_CTL			NSS_REG(0x3D74)
#define CE5_ACLK_SRC_CTL			NSS_REG(0x3D80)
#define CE5_ACLK_SRC0_NS			NSS_REG(0x3D84)
#define CE5_ACLK_SRC1_NS			NSS_REG(0x3D88)
#define CE5_ACLK_CTL				NSS_REG(0x3D8C)
#define PLL_ENA_NSS				NSS_REG(0x3DA0)
#define NSSTCM_CLK_SRC_CTL			NSS_REG(0x3DC0)
#define NSSTCM_CLK_SRC0_NS			NSS_REG(0x3DC4)
#define NSSTCM_CLK_SRC1_NS			NSS_REG(0x3DC8)
#define NSSTCM_CLK_FS				NSS_REG(0x3DCC)
#define NSSTCM_CLK_CTL				NSS_REG(0x3DD0)
#define CE5_CORE_0_RESET			NSS_REG(0x3E00)
#define CE5_CORE_1_RESET			NSS_REG(0x3E04)
#define CE5_CORE_2_RESET			NSS_REG(0x3E08)
#define CE5_CORE_3_RESET			NSS_REG(0x3E0C)
#define CE5_AHB_RESET				NSS_REG(0x3E10)
#define NSS_RESET				NSS_REG(0x3E20)
//#define GMAC_AHB_RESET				NSS_REG(0x3E24)
#define MACSEC_CORE1_RESET			NSS_REG(0x3E28)
#define MACSEC_CORE2_RESET			NSS_REG(0x3E2C)
#define MACSEC_CORE3_RESET			NSS_REG(0x3E30)
#define NSS_TCM_RESET				NSS_REG(0x3E40)
#define MVS_CNTRL				NSS_REG(0x3DF0)
#define CLK_TEST_NSS_REG			NSS_REG(0x2FA0)
#define GCC_APCS_CLK_DIAG			NSS_REG_GCC(0x001C)


#endif /* _GMAC_CLOCK_H_ */


